`timescale 10ns/1ps

module MUX_32to1_test;
	reg [31:0] D;
	reg [4:0] S;
	wire Y;
	
	MUX_32to1 U0(.*);
	
	initial fork
		D[2:0] <= 3'b101;
		S <= 5'b00000;
		#1 S<=5'b00001;
		#2 S<=5'b00010;
	join
	
endmodule